Open HDL cores for FPGA. License, tests and activity checked on GitHub.
MIT-licensed RISC-V CPU from SpinalHDL, successor of VexRiscv: RV32/64, optional SV32/SV39 MMU, Linux capable, written in SpinalHDL, generates Verilog.
CPUs and computeSpinalHDL (Scala)MITM2 · Simulation-testedupdated 9 days ago
Common Wishbone interconnect package.
Buses and infrastructureISCM2 · Simulation-testedupdated 8 months ago
CERN's library of common RTL components in VHDL-2008: memories, I/O, clock domain crossing, stream interfaces. Licence CERN-OHL-W-2.0.
Buses and infrastructureVHDL-2008CERN-OHL-W-2.0M1 · Prototype
Wishbone/AXI bridge and formal property library.
Buses and infrastructureVerilogNo license foundM2 · Simulation-testedupdated 26 days ago
OpenRISC core relevant to Wishbone history.
CPUs and computeVerilogNo license foundM4 · Production-readyupdated 4 months ago
CPU, Wishbone and formal-heavy ecosystem.
CPUs and computeVerilogNo license foundM2 · Simulation-testedupdated 21 days ago
Useful Wishbone-accessible debug core by ZipCPU author.
Verification and debugVerilogGPLM1 · Prototype
Verification helper for Wishbone cores.
Verification and debugNo license foundM2 · Simulation-testedupdated 9 years ago
Example of DSP cores with Wishbone and claimed FPGA evidence.
DSP and radioVHDLLGPLM1 · Prototype
Minimal SoC building block.
Memory and storageNo license foundM1 · Prototype
