Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| wb_intercon Buses and infrastructure | M2 · Simulation-tested | ISC | — | updated 8 months ago |
| colibri Buses and infrastructure | M1 · Prototype | CERN-OHL-W-2.0 | VHDL-2008 | — |
| ZipCPU wb2axip Buses and infrastructure | M2 · Simulation-tested | No license found | Verilog | updated 26 days ago |