Canonical UART reference and common FuseSoC adaptations.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
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Open HDL cores for FPGA. License, tests and activity checked on GitHub.
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Open HDL cores for FPGA. License, tests and activity checked on GitHub.
Canonical UART reference and common FuseSoC adaptations.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype