SERV
Checked on GitHubTiny RISC-V core and FuseSoC-friendly ecosystem.
CPUs and computeVerilogISCM4 · Production-readyupdated 43 days ago
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
CERN's library of common RTL components in VHDL-2008: memories, I/O, clock domain crossing, stream interfaces. Licence CERN-OHL-W-2.0.
Buses and infrastructureVHDL-2008CERN-OHL-W-2.0M1 · Prototype
Open Logic AXI/base/intf
Checked on GitHubFuseSoC-listed open logic package family.
Buses and infrastructureNo license foundM4 · Production-readyupdated 6 days ago
Canonical UART reference and common FuseSoC adaptations.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype