Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| opencores pwm Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores simple spi Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| OpenCores UART16550 Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |
| OpenCores Ethernet MAC Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |
| OpenCores I2C controller Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |
| OpenCores SPI master/slave Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |
| opencores can core Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores usbhostslave Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| IObundle Ethernet Interfaces and peripherals | M4 · Production-ready | CERN-OHL-S-2.0 | — | updated 16 days ago |
| IObundle UART16550 Interfaces and peripherals | M4 · Production-ready | No license found | — | updated 16 days ago |