Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| jotego jtcores Retro | M2 · Simulation-tested | GPL-3.0 | Verilog | updated 3 days ago |
| MiSTer SNES Retro | M2 · Simulation-tested | GPL-3.0 | — | updated 3 days ago |
| MiSTer NES Retro | M1 · Prototype | GPL-3.0 | — | updated 7 days ago |
| MiSTer ao486 Retro | M2 · Simulation-tested | No license found | — | updated 2 days ago |
| MiSTer Minimig Retro | M2 · Simulation-tested | No license found | — | updated 2 days ago |