Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| OpenCores WBScope Verification and debug | M1 · Prototype | GPL | Verilog | — |
Submit a core
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| OpenCores WBScope Verification and debug | M1 · Prototype | GPL | Verilog | — |