Useful Wishbone-accessible debug core by ZipCPU author.
Verification and debugVerilogGPLM1 · Prototype
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
Submit a core
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
Useful Wishbone-accessible debug core by ZipCPU author.
Verification and debugVerilogGPLM1 · Prototype