Useful Wishbone-accessible debug core by ZipCPU author.
Verification and debugVerilogGPLM1 · Prototype
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
wb_bfm
Checked on GitHubVerification helper for Wishbone cores.
Verification and debugNo license foundM2 · Simulation-testedupdated 9 years ago