Open-source FPGA projects | FPGA.camp

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Maintainedgithub.comMay 8, 2026Apache-2.0

Suite of SystemVerilog developer tools: parser, formatter, linter, and syntax tooling.

SystemVerilogLintFormatterParserOpen-source Verilog / SystemVerilog

Maintainedgithub.comApril 26, 2026LGPL-3.0 / Artistic-2.0

Open-source SystemVerilog simulator and lint system.

SystemVerilogC++SystemCLintOpen-source Verilator+1

Maintainedgithub.comApril 26, 2026ISC

Open SYnthesis Suite for Verilog RTL synthesis and formal-related flows.

VerilogRTLILSynthesisFormalOpen-source Yosys+1