Python-based FPGA SoC builder for cores, buses, soft CPUs, and board targets.
Projects
Yosys ecosystem projects
Open synthesis and PnR.
Portable FPGA place-and-route tool with support for several FPGA families.
Open SYnthesis Suite for Verilog RTL synthesis and formal-related flows.
Publication criteria
This catalog has few published projects. Only real records with a repository or verifiable source are shown; unverified projects are not created.
Repository URLLicense and statusMaintainer or source evidenceFPGA/RTL/tooling scope