Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | CORE-V-VERIF | LiteScope | OpenCores WBScope |
|---|---|---|---|
| Maturity | M4 · Production-ready | M2 · Simulation-tested | M1 · Prototype |
| License | No license found | No license found | GPL · Copyleft |
| Language | SystemVerilog/UVM | Migen/Python/Verilog | Verilog |
| Tests | yes | yes | — |
| CI | yes | yes | — |
| Formal | yes | — | — |
| FuseSoC | — | — | — |
| Activity | updated 23 days ago | updated 13 days ago | — |
| Boards | — | — | — |
| Interfaces | — | JTAG/debug | JTAG/debug, Wishbone |
| Category | Verification and debug | Verification and debug | Verification and debug |