Compare cores

Up to four cores side by side: maturity, license, tests and activity.

AttributefifoIObundle cacheLiteSDCardLiteSATA
MaturityM2 · Simulation-testedM1 · PrototypeM2 · Simulation-testedM2 · Simulation-tested
LicenseNo license foundCERN-OHL-S-2.0 · CopyleftNo license foundNo license found
Language——Migen/Python/VerilogMigen/Python/Verilog
Testsyes—yesyes
CI—yesyesyes
Formal————
FuseSoCyes———
Activityupdated 6 years agoupdated 16 days agoupdated 1 day agoupdated 9 days ago
Boards————
InterfacesFIFO/stream, MemoryMemorySD/SDIOSATA
CategoryMemory and storageMemory and storageMemory and storageMemory and storage