Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | opencores sdram controller | LiteSATA | IObundle cache | wb_ram |
|---|---|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested | M1 · Prototype | M1 · Prototype |
| License | No license found | No license found | CERN-OHL-S-2.0 · Copyleft | No license found |
| Language | Verilog/VHDL unknown until review | Migen/Python/Verilog | — | — |
| Tests | — | yes | — | — |
| CI | — | yes | yes | — |
| Formal | — | — | — | — |
| FuseSoC | — | — | — | — |
| Activity | — | updated 9 days ago | updated 16 days ago | — |
| Boards | — | — | — | — |
| Interfaces | Memory | SATA | Memory | Memory, Wishbone |
| Category | Memory and storage | Memory and storage | Memory and storage | Memory and storage |