Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | OpenCores WBScope | LiteScope | CORE-V-VERIF |
|---|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested | M4 · Production-ready |
| License | GPL · Copyleft | No license found | No license found |
| Language | Verilog | Migen/Python/Verilog | SystemVerilog/UVM |
| Tests | — | yes | yes |
| CI | — | yes | yes |
| Formal | — | — | yes |
| FuseSoC | — | — | — |
| Activity | — | updated 13 days ago | updated 23 days ago |
| Boards | — | — | — |
| Interfaces | JTAG/debug, Wishbone | JTAG/debug | — |
| Category | Verification and debug | Verification and debug | Verification and debug |