Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | OpenCores WBScope | wb_bfm | CORE-V-VERIF | LiteScope |
|---|---|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested | M4 · Production-ready | M2 · Simulation-tested |
| License | GPL · Copyleft | No license found | No license found | No license found |
| Language | Verilog | — | SystemVerilog/UVM | Migen/Python/Verilog |
| Tests | — | yes | yes | yes |
| CI | — | — | yes | yes |
| Formal | — | — | yes | — |
| FuseSoC | — | yes | — | — |
| Activity | — | updated 9 years ago | updated 23 days ago | updated 13 days ago |
| Boards | — | — | — | — |
| Interfaces | JTAG/debug, Wishbone | Wishbone | — | JTAG/debug |
| Category | Verification and debug | Verification and debug | Verification and debug | Verification and debug |