Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| OpenCores WBScope Verification and debug | M1 · Prototype | GPL | Verilog | — |
| OpenCores WDSP DSP and radio | M1 · Prototype | LGPL | VHDL | — |
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