Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| verilog-axi Buses and infrastructure | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| verilog-axis Buses and infrastructure | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| taxi Buses and infrastructure | M2 · Simulation-tested | CERN-OHL-S-2.0 | — | updated 40 days ago |
| ZipCPU wb2axip Buses and infrastructure | M2 · Simulation-tested | No license found | Verilog | updated 26 days ago |
| Open Logic AXI/base/intf Buses and infrastructure | M4 · Production-ready | No license found | — | updated 6 days ago |
| pulp-platform axi Buses and infrastructure | M4 · Production-ready | No license found | SystemVerilog | updated 13 days ago |
| VexiiRiscv CPUs and compute | M2 · Simulation-tested | MIT | SpinalHDL (Scala) | updated 9 days ago |
| colibri Buses and infrastructure | M1 · Prototype | CERN-OHL-W-2.0 | VHDL-2008 | — |
| Orthogone ULL PCIe circular-buffer DMA controller (Gen3/Gen4) Interfaces and peripherals | M1 · Prototype | Commercial license; encrypted RTL (closed source) | Verilog | — |
| Orthogone ULL 10G TCP/IP and UDP/IP Offload Engine Interfaces and peripherals | M1 · Prototype | Commercial license; encrypted RTL (closed source) | Verilog | — |
| Orthogone ULL Ethernet MAC/PCS 1G-100G with optional RS-FEC Interfaces and peripherals | M1 · Prototype | Commercial license; encrypted RTL (closed source) | Verilog | — |
| Efinix Sapphire RV64 SoC CPUs and compute | M1 · Prototype | No license found | — | — |