Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| SERV CPUs and compute | M4 · Production-ready | ISC | Verilog | updated 43 days ago |
| colibri Buses and infrastructure | M1 · Prototype | CERN-OHL-W-2.0 | VHDL-2008 | — |
| Open Logic AXI/base/intf Buses and infrastructure | M4 · Production-ready | No license found | — | updated 6 days ago |
| OpenCores UART16550 Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |