FPGA + SoC projects

Extensible waveform viewer for VCD/FST/GHW debug, available as native and web apps.

Suite of SystemVerilog developer tools: parser, formatter, linter, and syntax tooling.

Python-based FPGA SoC builder for cores, buses, soft CPUs, and board targets.

Open-source SystemVerilog simulator and lint system.

Open SYnthesis Suite for Verilog RTL synthesis and formal-related flows.