RISC-V FPGA projects

2 results

Topic: verilatorClear filters

Maintainedgithub.comApril 26, 2026BSD-2-Clause

Python-based FPGA SoC builder for cores, buses, soft CPUs, and board targets.

PythonMigenRISC-VSoCOpen-sourceLiteX

Maintainedgithub.comApril 26, 2026LGPL-3.0 / Artistic-2.0

Open-source SystemVerilog simulator and lint system.

SystemVerilogC++SystemCLintOpen-sourceVerilator+1

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Repository URLLicense and statusMaintainer or source evidenceFPGA/RTL/tooling scope