FPGA.camp opened its first version as a compact engineering hub: news, journal, projects, classifieds, meetups, boards, KB, and Chat.
8 results
Starter Tang board on Gowin GW1NR-9: 8640 LUT4, HDMI, TF slot, USB-JTAG, and USB-UART.
GW2AR-18 board: 20736 LUT4, SDR SDRAM, HDMI, TF slot, and BL616 debugger.
The /chat section accepts FPGA questions and sends them through a server-side OpenRouter endpoint.
The April 30, 2026 webinar compares when high-level code is enough and when dedicated hardware logic in Verilog is the right tool.
AMD’s new engineering article covers system-level verification for Versal designs that combine PL, AI Engines, NoC, and software.
The Vitis 2025.2 tutorial shows a system FIR flow for Versal with AI Engines, HLS, and programmable logic.
AN4792 describes a high-speed data transfer demo on PolarFire FPGA using LiteFast IP, 8b10b mode, and a loopback setup.