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Topic: verilator ×Clear all

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GitHub open-sourceGuideApril 25, 2026
Verilator: SystemVerilog simulator and lint

Verilator compiles Verilog/SystemVerilog into C++/SystemC and is used in regression flows.

Open-sourceVerilatorVerilog / SystemVerilog

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FPGA + SoC11Education8Verilog / SystemVerilog7Open-source5Gowin4Online4AMD / Xilinx3Lattice3Microchip3Sipeed3Verilator1
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Intel / Altera2Yosys2Efinix1LiteX1RISC-V1topic-fpga1topic-fpga-boards1topic-gowin1topic-open-fpga-synthesis1topic-open-source-eda1topic-tang-nano1topic-yosys1vendor-sipeed1

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