Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| VexiiRiscv CPUs and compute | M2 · Simulation-tested | MIT | SpinalHDL (Scala) | updated 9 days ago |
| wb_intercon Buses and infrastructure | M2 · Simulation-tested | ISC | — | updated 8 months ago |
| colibri Buses and infrastructure | M1 · Prototype | CERN-OHL-W-2.0 | VHDL-2008 | — |
| ZipCPU wb2axip Buses and infrastructure | M2 · Simulation-tested | No license found | Verilog | updated 26 days ago |
| OpenRISC mor1kx CPUs and compute | M4 · Production-ready | No license found | Verilog | updated 4 months ago |
| ZipCPU CPUs and compute | M2 · Simulation-tested | No license found | Verilog | updated 21 days ago |
| OpenCores WBScope Verification and debug | M1 · Prototype | GPL | Verilog | — |
| wb_bfm Verification and debug | M2 · Simulation-tested | No license found | — | updated 9 years ago |
| OpenCores WDSP DSP and radio | M1 · Prototype | LGPL | VHDL | — |
| wb_ram Memory and storage | M1 · Prototype | No license found | — | — |