Production candidates

Board-proven, or tested with a known license. The decision is still yours.

Caliptra RTL

Checked on GitHub

CHIPS Alliance root-of-trust IP.

CryptographyApache-2.0M4 · Production-readyupdated 1 day ago

OpenTitan KMAC IP

Checked on GitHub

Useful crypto/security reference.

CryptographyApache-2.0M4 · Production-readyupdated 1 day ago

OpenTitan prim library

Checked on GitHub

Primitive library reference.

Buses and infrastructureApache-2.0M4 · Production-readyupdated 1 day ago

OpenTitan IP blocks

Checked on GitHub

OpenTitan IP blocks with documentation and verification code.

CryptographySystemVerilogApache-2.0M4 · Production-readyupdated 2 days ago

SERV

Checked on GitHub

Tiny RISC-V core and FuseSoC-friendly ecosystem.

CPUs and computeVerilogISCM4 · Production-readyupdated 43 days ago

OpenTitan UART IP

Checked on GitHub

OpenTitan UART documentation.

Interfaces and peripheralsApache-2.0M4 · Production-readyupdated 1 day ago

OpenTitan AES IP

Checked on GitHub

Security IP block with documentation and test culture.

CryptographyApache-2.0M4 · Production-readyupdated 1 day ago

OpenTitan HMAC IP

Checked on GitHub

Crypto hash block with docs.

CryptographyApache-2.0M4 · Production-readyupdated 1 day ago

OpenTitan I2C IP

Checked on GitHub

I2C reference with docs.

Interfaces and peripheralsApache-2.0M4 · Production-readyupdated 1 day ago

OpenTitan SPI device IP

Checked on GitHub

SPI device reference.

Interfaces and peripheralsApache-2.0M4 · Production-readyupdated 1 day ago

Amaranth HDL

Checked on GitHub

Modern Python-based HDL ecosystem source.

Generators and frameworksBSD-2-ClauseM4 · Production-readyupdated 19 days ago

NEORV32

Checked on GitHub

Well-documented VHDL RISC-V SoC candidate.

CPUs and computeVHDLBSD-3-ClauseM4 · Production-readyupdated 3 days ago

IObundle Ethernet

Checked on GitHub

Ethernet candidate with OpenCores ethmac relation.

Interfaces and peripheralsCERN-OHL-S-2.0M4 · Production-readyupdated 16 days ago

LiteX

Checked on GitHub

Central open SoC builder and integration framework.

Generators and frameworksMigen/Python/VerilogCustom licenseM4 · Production-readyupdated 7 days ago

OpenHW CVA6

Checked on GitHub

Linux-capable RISC-V core lineage.

CPUs and computeSystemVerilogNo license foundM4 · Production-readyupdated 3 days ago

pulp-platform common_cells

Checked on GitHub

Reusable cells widely used by PULP projects.

Buses and infrastructureSystemVerilogNo license foundM4 · Production-readyupdated 19 days ago

OpenHW CV32E40P

Checked on GitHub

Specific CORE-V core with verification evidence.

CPUs and computeSystemVerilogNo license foundM4 · Production-readyupdated 6 days ago

CORE-V-VERIF

Checked on GitHub

Verification evidence model for CORE-V cores.

Verification and debugSystemVerilog/UVMNo license foundM4 · Production-readyupdated 23 days ago

Open Logic AXI/base/intf

Checked on GitHub

FuseSoC-listed open logic package family.

Buses and infrastructureNo license foundM4 · Production-readyupdated 6 days ago

pulp-platform axi

Checked on GitHub

AXI components and infrastructure.

Buses and infrastructureSystemVerilogNo license foundM4 · Production-readyupdated 13 days ago

OpenRISC mor1kx

Checked on GitHub

OpenRISC core relevant to Wishbone history.

CPUs and computeVerilogNo license foundM4 · Production-readyupdated 4 months ago

IObundle UART16550

Checked on GitHub

Modern adaptation of OpenCores UART16550.

Interfaces and peripheralsNo license foundM4 · Production-readyupdated 16 days ago

Wally RISC-V

Checked on GitHub

Open RISC-V core family for comparison.

CPUs and computeSystemVerilogNo license foundM4 · Production-readyupdated 4 days ago

hdl-util HDMI

Checked on GitHub

Open HDMI/DVI transmitter candidate.

Audio and videoVerilog/VHDLNo license foundM4 · Production-readyupdated 3 months ago

VexiiRiscv

Checked on GitHub

MIT-licensed RISC-V CPU from SpinalHDL, successor of VexRiscv: RV32/64, optional SV32/SV39 MMU, Linux capable, written in SpinalHDL, generates Verilog.

CPUs and computeSpinalHDL (Scala)MITM2 · Simulation-testedupdated 9 days ago

Ibex

Checked on GitHub

Small open RISC-V CPU used by OpenTitan.

CPUs and computeSystemVerilogApache-2.0M2 · Simulation-testedupdated 5 days ago

BlackParrot

Checked on GitHub

Manycore RISC-V candidate.

CPUs and computeBSD-3-ClauseM2 · Simulation-testedupdated today

uart verilog by alexforencich

Checked on GitHub

Common GitHub UART implementation.

Interfaces and peripheralsMITM2 · Simulation-testedupdated 2 years ago

LiteSPI

Checked on GitHub

Common SPI/SPI flash block in LiteX designs.

Interfaces and peripheralsMigen/Python/VerilogBSD-2-ClauseM2 · Simulation-testedupdated 13 days ago

VexRiscv

Checked on GitHub

Configurable RISC-V softcore used in LiteX ecosystem.

CPUs and computeSpinalHDL/Scala/VerilogMITM2 · Simulation-testedupdated 10 days ago

wb_intercon

Checked on GitHub

Common Wishbone interconnect package.

Buses and infrastructureISCM2 · Simulation-testedupdated 8 months ago

verilog-axi

Checked on GitHub

AXI component library and comparison source.

Buses and infrastructureMITM2 · Simulation-testedupdated 2 years ago

verilog-axis

Checked on GitHub

AXI-Stream component library.

Buses and infrastructureMITM2 · Simulation-testedupdated 2 years ago

verilog-ethernet

Checked on GitHub

Ethernet MAC/UDP/IP stack candidate.

Interfaces and peripheralsMITM2 · Simulation-testedupdated 2 years ago

stream_utils

Checked on GitHub

Stream FIFO/width conversion baseline.

Buses and infrastructureISCM2 · Simulation-testedupdated 12 months ago

PicoRV32

Checked on GitHub

Compact softcore with strong FPGA relevance.

CPUs and computeVerilogISCM2 · Simulation-testedupdated 30 days agoarchived