Cores

Open HDL cores for FPGA. License, tests and activity checked on GitHub.

Submit a core

23 results

CoreMaturityLicenseLanguageActivity
VexiiRiscv
CPUs and compute
M2 · Simulation-testedMITSpinalHDL (Scala)updated 9 days ago
Ibex
CPUs and compute
M2 · Simulation-testedApache-2.0SystemVerilogupdated 5 days ago
BlackParrot
CPUs and compute
M2 · Simulation-testedBSD-3-Clause—updated today
SERV
CPUs and compute
M4 · Production-readyISCVerilogupdated 43 days ago
NEORV32
CPUs and compute
M4 · Production-readyBSD-3-ClauseVHDLupdated 3 days ago
VexRiscv
CPUs and compute
M2 · Simulation-testedMITSpinalHDL/Scala/Verilogupdated 10 days ago
PicoRV32
CPUs and compute
M2 · Simulation-testedISCVerilogupdated 30 days ago
ultraembedded riscv
CPUs and compute
M2 · Simulation-testedBSD-3-Clause—updated 5 years ago
BOOM
CPUs and compute
M1 · PrototypeBSD-3-Clause—updated 26 days ago
OpenHW CORE-V cores
CPUs and compute
M1 · PrototypeSolderpadSystemVerilogupdated 6 months ago
OpenHW CVA6
CPUs and compute
M4 · Production-readyNo license foundSystemVerilogupdated 3 days ago
OpenHW CV32E40P
CPUs and compute
M4 · Production-readyNo license foundSystemVerilogupdated 6 days ago
ultraembedded core_soc
CPUs and compute
M1 · PrototypeGPL-2.0—updated 6 years ago
OpenRISC mor1kx
CPUs and compute
M4 · Production-readyNo license foundVerilogupdated 4 months ago
ZipCPU
CPUs and compute
M2 · Simulation-testedNo license foundVerilogupdated 21 days ago
Wally RISC-V
CPUs and compute
M4 · Production-readyNo license foundSystemVerilogupdated 4 days ago
Berkeley HardFloat
CPUs and compute
M2 · Simulation-testedNo license found—updated 2 months ago
Rocket Chip
CPUs and compute
M1 · PrototypeNo license found—updated 24 days ago
Efinix Sapphire RV64 SoC
CPUs and compute
M1 · PrototypeNo license found——
OpenHW CV32E40S
CPUs and compute
M2 · Simulation-testedNo license found—updated 2 years ago
OpenHW CV32E40X
CPUs and compute
M2 · Simulation-testedNo license found—updated 2 years ago
OpenRISC or1200
CPUs and compute
M2 · Simulation-testedNo license foundVerilogupdated 11 years ago
opencores minsoc
CPUs and compute
M1 · PrototypeNo license foundVerilog/VHDL unknown until review—